Semiconductor devices are fabricated by creating a sequence of patterned and un-patterned layers where the features on patterned layers are spatially related to one another. Thus during fabrication, each patterned layer must be aligned with a previous patterned layer, and as such, an overlay (layer-to-layer alignment) between a first layer and a second layer must be taken into account. As semiconductor processes evolve to provide for smaller critical dimensions and devices reduce in size and increase in complexity including number of layers, an alignment precision between layers becomes increasingly more important to the quality, reliability and yield of the devices. Misalignment of layers can cause performance issues and even potentially cause a device to fail due to, for example, a short caused by a misaligned interconnect layer. An overlay error may be induced by using different exposure tools to expose different layers. It is desired to have improvements in this area.